1. Field of the Disclosure
This disclosure relates to a method of manufacturing through-glass vias and, in particular, top and bottom channeling of a glass substrate where the top channels and bottom channels are orthogonal or non-orthogonal to each other, and form aligned holes at the point of intersection, with the holes together forming a through-glass via hole.
2. Discussion of the Background Art
In microelectronics, integrated circuit device density is increasing at a high rate. The number of transistors per chip continues to grow. However, the embodiment of further miniaturization of integrated circuits is costly and the ever more complex circuits require an increasing number of I/O leads, which complicates the contacting and packaging of the devices. Hence, other means for getting higher device density are needed. An emerging alternative is to increase the device density per unit area by stacking devices on top of each other. Currently, stacked devices are mostly interconnected by wire bonding, which is a complex process that requires a large amount of space on the device and unnecessarily long connecting leads. Furthermore, wire bonding commonly gives a fairly high resistance and can be unreliable.
Related to microelectronics are microelectromechanical systems (MEMS), in which the functionality of the microelectronic systems or technologies can be enhanced. In MEMS, integrated circuits are integrated with, e.g., mechanical, chemical, biological functions, or, based on the vast knowledge of microelectronic processing, microelectromechanical systems such as accelerometers, sensors, or biochips are manufactured. Many of these microelectromechanical systems extended in all 3 dimensions in order to obtain the desired functionalities.
As in microelectronics, MEMS structures are mainly fabricated using silicon wafers as substrates, but, e.g., other semiconducting materials, polymers, ceramics and glass are becoming more widely used. Accompanying the increasing interest in making 3D microelectronic and MEMS structures, there is an increasing interest in making electrical interconnects between the front side and the back side of the substrates or wafers of the 3D structure, i.e., so called “through-wafer vias”. Using these, unreliable and costly wire bonding is avoided and the interconnect density can be increased. The through-wafer vias should occupy as small area as possible on the wafers and the resistance of the electrical interconnects should be low. Furthermore, the processing of the through wafer vias should be compatible with conventional processing technologies in the field.
Different through-wafer via designs have been disclosed, and the strategy for making the via can be divided into two categories. In the first category, the through-wafer vias are formed by the wafer material, e.g., a doped semiconductor via. In the second category, a through-wafer via hole is formed in the wafer using, for example, laser ablation, drilling, wet etching or dry etching. Thereafter, a conductive material is deposited, e.g., using a physical vapour deposition (PVD) process, on at least the sidewalls of the through-wafer via hole. To increase the cross sectional area of the conductive through-wafer via (in order to reduce the electrical resistance) a metal or metal alloy is commonly plated onto the conductive coating. Through-wafer vias of the first category generally have a relatively high resistance as compared to through-wafer vias of the second category due to the higher conductivity of the metal or metal alloy.
The technique used for the formation of the via hole mainly depends on the wafer material. Silicon is used as an interposer having through-hole electrodes now. Silicon is relatively easily subjected to microfabrication by dry etching. However, since silicon is semiconductor, an inner wall of the through-holes has to be subjected to insulating treatment in order to secure the insulating property. Glass is being considered as an interposer. The advantages of glass include good insulation, matched CTE, smooth uniform surface, low dielectric constant, and low cost materials. However, it is difficult and expensive to form through-holes through a glass substrate, e.g., it is usual to use laser, sandblasting or ultrasonic wave drill to form through holes. In such a case, it is difficult and expensive to form micro through-holes, and the application of such a glass substrate is limited now.
The microelectronics industry has had a great deal of trouble forming good via holes inexpensively. As mentioned above, numerous methods have been tried with glass substrates including mechanical techniques such as drilling or sand blasting, chemical methods such as wet etching and photo sensitive glass, laser ablation methods, and electrical discharge methods. Via holes have been produced, but the complexity and cost structure of generating the through-via hole in a glass substrate are major obstacles. Low cost with very high reliability is an absolute driver for the microelectronics industry, especially the production of glass substrates having through-glass via holes for use as interposers.
There is a need to provide a glass substrate having a plurality of through-glass via holes suitable for various semiconductor devices, e.g., useful as an interposer. There is a need to provide a low cost, low complexity and high reliability method for producing a glass substrate having a plurality of through-glass via holes such that the glass substrate can be used as an interposer.
The present disclosure also provides many additional advantages, which shall become apparent as described below.